Semiconductor devices or “ICs” (integrated circuits) have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of semiconductor wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed.
An example of such a limit is the ability to accurately monitor temperatures in an efficient manner for rapid thermal anneal processes (RTP). RTP is important for any type of semiconductor wafer processing which requires precise temperature control and fast ramp up rate of the temperature. Consequently, RTP must be carried out in a specially-designed rapid thermal annealing (RTA) chamber, rather than in a conventional semiconductor wafer furnace having walls and other components characterized by high thermal conductivity that would hinder rapid thermal cycling. RTA chambers that use radiant heating are designed to thermally isolate a semiconductor wafer such that radiant, rather than conductive, heat is used in semiconductor wafer processing. As a result, all portions of the wafer are more uniformly heated, thereby eliminating or at least reducing thermal gradients which would otherwise cause wafer slip and warping. However, in order for the RTP to provide a high manufacturing yield, the temperature of the wafer must be accurately monitored, or the semiconductor device will not have the expected characteristics. Various design challenges make accurate temperature measurement difficult. In particular, the temperature is a result of the thermal absorption properties of the semiconductor device. However, the semiconductor device does not heat uniformly. Different exposed material on the semiconductor wafer has different reflectivity and hence absorbs different amounts of radiative heat. For example, in a typical semiconductor device, there is a silicon substrate with portions covered by oxide, typically corresponding to the isolation area between transistors on the silicon substrate. Also, there are portions where the crystalline silicon is the exposed surface, and there are portions where the poly-crystalline silicon constitute the exposed surface. Hence the pattern density (that is, the ratio of silicon covered with oxide or poly-crystalline silicon to exposed silicon over a given area) affects the thermal absorption, which is in turn affected by the temperature that the semiconductor reaches during the RTP. This temperature depends on the application, but can be beyond 1,000 degrees Centigrade.
What is needed is a relatively inexpensive structure, method and system for monitoring and characterizing the dependence thermal absorption on these various pattern densities of a various rapid thermal process.